This invention relates generally to the field of analog to digital converters and more particularly to a pipelined charge-mode analog to digital converter suitable for integration with other charge-mode devices.
Analog to digital (A/D) converters are well known in the electronics art for converting analog signals to a digital representation of the analog signal primarily to permit digital processing, digital storage, and/or digital display of the signal. A typical type of prior art A/D converter utilizes a plurality of analog comparators that compare an analog input voltage to reference voltages and generate binary bits in accordance with the results of the comparison. Such voltage A/D converters do not convert the magnitude of a charge packet to a digital representation, but instead generate a digital representation of an input analog voltage. However, many analog devices (including sensors and charge couple devices), are charge-mode devices which provide an output which is in the form of a charge packet. Such prior art voltage A/D converters require additional charge to voltage converters to permit them to be used with charge-mode devices. The charge to voltage converters introduce additional error, power consumption, and complexity. Thus, prior art voltage A/D converters are not highly suitable for use in a charge-mode environment.
Charge-mode A/D converters are known in the art using ramp or successive approximation techniques. The ramp type A/D converters generate a digital representation of a charge packet by decreasing the depth of a potential well containing the signal charge in a step wise fashion and test each step for an overflow of the charge. This type of A/D converter tends to be slow, results in a loss of the input charge packet, is difficult to fabricate to provide accurate results, and is highly susceptible to environmental influences such as ionizing radiation. The successive approximation type of charge-mode A/D converter uses a plurality of serial digitizing stages. Each stage generates a successively lower order digital bit by comparing a reference charge to the signal charge packet and generating a binary digit in accordance with the result of the comparison. The prior art successive approximation charge-mode A/D converters are complex and difficult to fabricate so as to produce accurate results, are sensitive to threshold shifts, and susceptible to environmental factors, such as ionizing radiation.
Accordingly, it is an object of this invention to provide a novel high-speed and accurate charge-mode A/D converter.
It is another object of this invention to provide a novel symmetric successive approximation charge-mode A/D converter which operates in high speed pipelined mode and avoids non-linear summing inaccuracies.
It is another object of the invention to provide a novel symmetric, single-channel, successive approximation charge-mode A/D converter which substantially reduces inaccuracies due to threshold variations.
It is another object of the invention to provide a novel differential symmetric successive approximation charge-mode A/D converter with enhanced accuracy, speed, and radiation hardness.
Briefly, according to one embodiment of the invention, a charge-mode A/D converter is provided to permit direct conversion of a charge packet to a digital output word. The analog to digital converter comprises a signal charge input to provide for input of a signal charge into a charge channel having a plurality of serially coupled charge wells. A charge injection circuit is provided for selectively generating and injecting predetermined charges, including a reference charge into the charge channel. A two-step comparator is coupled to the charge channel for sensing the signal charge and the reference charge, and then comparing the signal charge and reference charge to generate a control signal responsive to the comparison. Means are provided for selectively adding a selected charge to the reference charge and switch means is provided for conditionally adding a selected charge to the signal charge responsive to the control signals. A digital channel is provided for generating a digital word responsive to the control signals.
In an alternative embodiment, a differential symmetric charge-mode analog to digital converter is provided including means configured in stages for carrying first and second substantially equivalent and independent streams of reference and signal charges sequentially from stage to stage. A comparator is provided for simultaneously comparing the signal to the reference charge from the first independent stream, and the reference to the signal charge from the second independent stream for each stage and for generating control signals in response thereto. Control circuitry is provided for controlling conditional addition of a selected charge to the signal charge at each stage and in each stream responsive to the control signals, and a digital channel is provided for generating a digital word representative of the signal charge responsive to the control signals.